1. Field of the Invention
The invention disclosed herein relates generally to measurement of device parameter of an integrated circuit device in the device manufacturing process. More particularly, this invention relates to a new and more accurate measurement configuration and process to more conveniently obtain accurate device parameters on the wafer level of a semiconductor device.
2. Description of the Prior Art
With the advent of high-speed metal oxide semiconductor (MOS) gate devices for power-switching applications comes the need to accurately measure the equivalent series gate resistance (Rg). FIG. 1A shows the equivalent circuit of a metal oxide semiconductor field effect (MOSFET) based power device that comprises many MOSFET transistor cells. FIG. 1B shows this equivalent series gate resistance is in a series connection relationship with the input capacitance of the MOSFET to form an R-C network. Therefore, the series equivalent gate resistance cannot be measured by direct DC methods. Several AC methods are available to make this measurement. However, all of these methods require the calibration and cancellation of parasitic parameters inevitably arising from the testing circuits and cabling. Particularly, these cabling parasitic parameters are usually more difficult to deal with at the wafer level, since the die must be accessed through long cables connected between the testers and the probe card, and then via probes reaching to the die itself. Furthermore, as shown in FIG. 2, before a sawing operation is carried out on the wafer, the entire back plain of the wafer forms the second power electrode in a vertical device, and is accessed through similar long cables connected to the wafer chuck. Since the wafer chuck matches the wafer diameter, and may be four to twelve inches in diameter, this leads to considerable parasitic capacitance and inductance.
It is easier to measure the gate resistance at a final testing point after the MOS device is packaged. However, it is much more costly to reject a packaged device at the final test point. The loss caused by a rejected device at the final testing point includes the total cost of all the processes performed on the die and the package. For this reason, it is much more cost effective to screen out a potentially defective device at the wafer level. Cost savings are achieved by eliminating these unnecessary additional efforts and time spent on packaging these defective devices if the defective devices can be screened out at an earlier stage at the wafer level. Therefore, there exists a need to measure the device parameters as early as possible at the wafer level.
There are several alternate methods to calibrate and measure the equivalent gate resistance. FIG. 3 shows a configuration to carry out a direct AC testing method that uses an LCR meter for measuring the circuit impedance. The gate of a MOSFET device, i.e., the device under test (DUT), is treated as a simple R-C network. The gate resistance is measured using an LCR meter with a four-wire technique. An AC sinusoidal signal is applied to the device and the AC voltage, AC current and the phase difference is measured across the device. Then the impedance measurement is separated into a real part and an imaginary part with the real part representing the equivalent gate resistance Rg.
FIG. 4A shows another testing configuration to carry out a series resonance measurement. Since the device is a series RC network, a series inductance is introduced to create an RLC network as shown in FIG. 4A. By applying a frequency sweep across this network as that shown in FIG. 4B, a network impedance Z(ω) can be expressed as Z(ω)=Rg+j*[ωLs−(1/ωCiss)]. The capacitive impedance (1/ωCiss) and the inductive impedance ωLs cancel each other at the resonant frequency ωr when ωr=1/(Ls*Ciss)1/2. A net-impedance is obtained and that is the equivalent gate resistance Z(ωr)=Rg.
In reality, the implementation of both methods is complicated by the fact that the device behaves quite differently from a standard behavior of a simple RC network due to the existence of several parasitic parameters. When a direct AC method is applied, attention must be paid to the series inductance of the gate source network that arises from the die layout, the probe connections and the probe card and the cabling to the tester. Additionally, there are parasitic capacitances generated from connections of the cabling, the probe card, the probes, and the wafer chuck.
Normally, a simple open-short cancellation technique is available to deal with the parasitic effects. First, the probes are lifted up and the probes are disconnected from the Device Under Test (DUT). The impedance is measured and is used to determine the parasitic capacitance. Next, the probes are put down on a metal plane, with the probes shorted onto the wafer or the chuck, and the impedances are measured. The impedance measurement is used to determine the series parasitic resistance and inductance. However, in the first measuring step, it fails to correctly account for the chuck capacitance, while in the second measuring step, it fails to correctly account for the layout inductance. For these reasons, the cancellation techniques still do not provide an effective method to eliminate measurement errors caused by parasitic capacitances and inductances of wafer level measurements due to multiple cabling, probe card and probe connections and interfaces. In order to further improve the measurement accuracy, an additional correction known as load correction is applied by measuring a known R-C network. A printed circuit board (PCB) with predefined combination of resistance and capacitance is measured to carry out the additional process of load correction to enhance the measurement accuracy. However, this process can not eliminate probe card and die layout effects, because the PCB is not accessed through the same probe configuration.
Therefore, a need still exists in the art to provide an improved device design and test configurations and methods to overcome the above discussed limitations and difficulties.